The integration of digital and RF components in densely routed architectures requires careful layout design to ensure adequate DC or mixed-signal isolations in compliance with specifications for a particular application. To meet the emerging need to downscale complex multifunctional integrated circuit packages, layout routing techniques, packaging design and isolation methods have become very critical design considerations [1], [2].
Currently, common practices are set to place different electronic components including signal traces, circuits and conductors physically apart so as to minimize Electro-magnetic (EM) coupling. Additional measures including via-fencing and metal castings or walls are also employed to improve EM isolation. For example, in conventional Monolithic Microwave Integrated Circuit (MMICs) or Radio-Frequency (RF) packages, guard traces and via-fences are used to protect the mixed-signal traces/packages from stray radiation.
Via-fencing is a technique used for RF isolation by extending the ground plane up to the plane of the IC that contains the mixed-signal traces. Specifically, the ground trace on the ground plane is coupled to the guard trace on the plane of the IC using vias extending through the substrate. The vias may be metal-lined or metal-filled to effectively connect the guard trace to the ground plane. Depending on RF isolation requirements, via-fences with a suitable catch pad can be designed with various sizes and dimensions. Design rules for such structures are well known. For example, the design rules are correlated to a few factors, such as the physical and material properties of the substrate (e.g. relative permittivity, thickness), and design requirements (e.g. width of the signal traces). The database for such design rules is also well known [3].
Although the via-fencing technique is known to be effective in RF isolation, its use is limited to packages or ICs without space constraints. In particular, there is a minimal amount of space required between the via-fenced guard trace and the signal trace before good isolation between the signal traces or ICs can be achieved and the signal integrity can be maintained [3], [4]. Therefore, this solution has limitations for designs with limited real estate and/or tightly coupled mixed-signal traces or ICs in close proximity. This problem becomes even more prominent in high speed applications and/or high density circuitries.
The second technique involves mounting and aligning metal castings or walls to surround the electronic components/ICs on the substrate and compartmentalize the various electronic components fabricated/mounted on the substrate. The metallic walls may screen stray electromagnetic radiation and provides mechanical protection for the package. However, to date such metallic walls can only be built separately by casting or molding [5]. The metallic walls are then assembled onto the packages such as MMICs. Existing surface micromachining techniques used in microelectronic processes are generally not available to build such metallic walls because those techniques usually have very limited build-up thickness for metals. For example, solid metallic walls structures with a high aspect ratio (i.e. height/thickness of the wall), such as metal pillars having an aspect ratio greater than two, are not achievable by existing surface micromachining techniques used in microelectronics processes.
Accordingly, surface-mounting (conventional or flip-chip) or cavity-mounting are typically required for MMIC hybrid assemblies. In additional, complex alignment procedures and bonding techniques are usually necessary which lead to increased costs. More importantly, the post design integration of metal castings or walls often requires large space allowances for placement, which is undesirable for space-efficient considerations. In all, it is not cost effective to carry out both a post-mounting/alignment process of metal castings for EM shielding, and to customize individual molds of metal castings for different partitioning designs.
In summary, the existing solutions for providing good electrical isolation in a highly compact device are far from satisfactory. Via fences are used to surround the signal traces or ICs to reduce stray radiation. However, this method is not space and cost effective for implementing miniaturized multifunctional designs, especially for high speed signals. Metal castings are used to partition the components mechanically and protect them from unwanted EM interferences. However, the processes of mounting and aligning such metal castings are costly, complex and require buffer mounting areas, which again, is not space and cost efficient.